The present invention relates to a phase displaced resonant transition circuit which implements zero-voltage switching, and more particularly to a circuit maintaining constant resonant transition current from 0.degree. phase angle to 180.degree. phase angle in a full bridge configration.
As electronic equipment is continuously being miniaturized the power supplies used by such equipment must necessarily also be reduced in size. In order to accomplish the size reduction, designers are developing systems with increased switching frequencies allowing the use of smaller sized components. Also being used are newly developed topologies, such as resonant-mode supplies employing zero-voltage switching which are useful in decreasing power losses and radio frequency noise that normally occur at higher frequency switching. This zero-voltage switching is accomplished when a switch begins conduction near zero-voltage across the switch.
As switching frequencies are climbing to one MHz and beyond, the power supplies being used must produce an increasing amount of power while taking up less space, causing the power density to increase dramatically. In this environment there is, therefore, a crucial need to improve the efficiency of the power supplies.
At the component level, the technologies are already in place to take switching frequencies into the MHz region. Power FETs are the preferred switching device over bipolar transistors. FETs simplify dealing with magnetic saturation as they do not store charge, which results in a decrease in their switching transition time by more than an order of magnitude over bipolar transistors. Additionally, destructive secondary breakdown is avoided, which is inherent in bipolar transistors and, therefore, reduces or even eliminates the need for speed limiting snubber circuitry.
Many resonant zero-voltage switching circuitry topologies have been described including those discussed in Steigerwald, et al. U.S. Pat. No. 4,864,479; Jain U.S. Pat. No. 5,157,593; Walters U.S. Pat. No. 5,157,592; and the article entitled "High Performance 600 Watt Power Supply Features Phase Shifted Resonant PWM Control Technique" by Bill Andreycak and references cited within these patents and article.
It is noted that at the moment of turn-off of each switch of a resonant transition circuit, there needs to be present in that switch a lagging current of sufficient amplitude and duration to cause the voltage on that switch to rise to the amplitude of the supply in a totally passive fashion. At heavier loads, this current will be present in the series inductance of the power transformer. At light loads, the current may be obtained from energy stored in the shunt inductance of the power transformer. However, as a load approaches no-load and the phase angle approaches 0.degree., the volt-seconds applied to the power transformer primary approaches zero, and thereby the energy stored in the power transformer primary which is available as lagging current for resonant transition also approaches zero causing resonant transition to fail.
FIG. 1 shows a phase shifted full bridge converter with FET switches Q1, Q2, Q3 and Q4 operating at a fixed frequency. In order to lower the power dissipation in this circuit zero-voltage techniques are implemented, where a switch begins conduction with a near zero-voltage existing across the switch. To accomplish zero-voltage switching over a large range of line voltages and loads, the inductive currents carried by the switching devices are increased which in turn increases the conduction losses of the power devices and, therefore, provides very little gain in overall efficiency.
The on time of the diagonally conducting switches in FIG. 1 is not varied as in a PWM bridge circuit, rather the switches in a first leg (Q1 and Q2) and a second leg (Q3 and Q4), are made to conduct at a duty cycle approaching 50%. The phase shift between the operation of the switches in each of the legs determines when the diagonal switches Q2 and Q3 or Q1 and Q4 are conducting at the same time and, therefore, supplying power to a load. By varying the phase shift, the resulting output voltage can be pulse width modulated.
The transformer primary current flowing at turn-off of one transistor charges the parasitic capacitances of that transistor while reducing the charge on the parasitic capacitances of the other transistor in the same leg, thereby reducing the voltage across the other transistor, which is also the next transistor to be turned on. To obtain zero-voltage switching requires that the turn-on of the transistor in the same leg with the transistor that was just turned off must be delayed until the voltage across the transistor to be turned on has been reduced to near zero. For a pair of transistors in the same leg, the time required to charge the capacitances of the transistor being turned off and discharge the parasitic capacitance of the transistor to be turned on, is inversely proportional to the magnitude of current established before the switching interval.
Transistors Q1 and Q2 are turned on after a freewheeling period when current was being circulated in the bridge and the current established before switching is the current circulating in the transformer primary T.sub.P during the freewheeling interval. The freewheeling interval is the portion of each cycle when no energy is being supplied to the output load L connected with filter capacitor C.sub.f and choke coil C.sub.c, from the input power source Vin. The transformer leakage inductance is the energy source displacing charge on the parasitic capacitances of transistors Q1 and Q2, where the magnitude of energy is proportional to the square of the circulating current.
The circulating current will decay during the freewheeling interval, as a result of both output rectifiers R.sub.1, R.sub.2, which are connected to the two ends of the transformer secondary T.sub.s, conducting current and reducing the energy stored in the leakage inductance, and as a result of Q1-Q4 R.sub.ds (i.e. drain to source losses on losses as well as intrinsic diode losses in Q1-Q4. The circulating current is equal to the difference in output rectifier currents divided by the turns ratio of the transformer. With both output rectifiers carrying equal current, the transformer primary current would be zero, resulting in no energy available in the transformer leakage inductance to charge the parasitic capacitances of the transistor to be turned on, and for this condition, zero-voltage switching would not be achieved. The magnitude of the circulating current is always less than the reflected output inductor current when power is being delivered to the load. Therefore, zero-voltage switching is more difficult to achieve with transistors Q1 and Q2, which are turned on after circulating current was flowing in the bridge.
One approach to maintain zero-voltage switching is to increase the magnitude of the leakage inductance. This will reduce the magnitude of the current decay during the freewheeling interval. Additional leakage inductance will also increase the energy available for displacing charge on the transistor's output capacitances. With this approach, a minimum leakage inductance can be specified to meet zero-voltage switching requirements for a specific line and load condition. However, the high leakage inductance will reduce the effective duty cycle ratio to the transformer secondary due to the increased recovery time of the output diodes. This will limit the input voltage range of the converter and adversely affect the voltage control characteristics.
Another approach for achieving zero-voltage switching over a wide input line and output load range uses saturable reactors with specific blocking characteristics. A saturable reactor is used in series with each push-pull output rectifier. This technique uses a round or flat B-H loop reactor core material to induce a significant flux excursion during the output rectifier commutating interval. The reactor will provide a blocking characteristic proportional to the flux excursion. The blocking characteristic of the reactor together with a clamped primary prevents the conduction of both rectifiers during the freewheeling interval. This forces the circulating inductor to follow the output inductor current. Therefore, more energy is available to displace the transistor's parasitic capacitance charge. However, for a converter to achieve zero-voltage switching at a light load, the saturable core must be designed to block the entire freewheeling interval. At full load, more than the required energy for zero-voltage switching is available, and as a consequence, transistor conduction losses are increased.
None of the above cited material describe a method and/or circuit where a constant resonant transition current is obtained from 0.degree. phase angle to 180.degree. in no-load to full-load situations for a full bridge phase displaced resonant transition circuit and which also limits the core losses of a power transformer to substantially a single core loss.
The present invention provides a new and improved full bridge phase displaced resonant transition circuit and method which overcomes the above referenced drawbacks and others.